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Project title: |
Experienced ASIC/FPGA Designer and Technological Lead
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Posted by: |
External project from Freelancer
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Started: |
08-Dec-2024 10:41 GMT |
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Description: |
Spyglas,VCS,DC,DFT,Verdi,Catapult,Synplify,VerilogXL,Virtuoso,Xcelium,Spectre,Allegro,Vivado,Quartus,ModleSim, Matlab,Octave,Signal Generator,Logic Analyzer,Anaconda,Tensorflow,Keras,Darknet ,notepad++... (Budget: $25 - $50 USD, Jobs: C Programming, Electrical Engineering, Electronics, Microcontroller, Verilog / VHDL) |
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Project ID:
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3411699 |
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Project category: |
C, Programming, Electrical Engineering, Electronics, Microcontroller, Verilog / VHDL |
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Project budget: |
$25 - $50 USD |
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